@ARTICLE{Kolasinski_Piotr_Zero-Suppression_2021,
 author={Kolasinski, Piotr and Pozniak, Krzysztof and Wojenski, Andrzej and Linczuk, Paweł and Krawczyk, Rafał and Gaska, Michał and Zabolotny, Wojciech and Kasprowicz, Grzegorz and Chernyshova, Maryna and Czarski, Tomasz},
 volume={vol. 67},
 number={No 1},
 journal={International Journal of Electronics and Telecommunications},
 pages={103-108},
 howpublished={online},
 year={2021},
 publisher={Polish Academy of Sciences Committee of Electronics and Telecommunications},
 abstract={A novel approach to a trigger mode in the Gas Electron Multiplier (GEM) detector readout system is presented. The system is already installed at WEST tokamak. The article briefly describes the architecture of the GEM detector and the measurement system. Currently the system can work in two trigger modes: Global Trigger and Local Trigger. All trigger processing blocks are parts of the Charge Signal Sequencer module which is responsible for transferring data to the PC. Therefore, the article presents structure of the Sequencer with details about basic blocks, theirs functionality and output data configuration. The Sequencer with the trigger algorithms is implemented in an FPGA chip from Xilinx. Global Trigger, which is a default mode for the system, is not efficient and has limitations due to storing much data without any information. Local trigger which is under tests, removes data redundancy and is constructed to send only valid data, but the rest of the software, especially on the PC side, is still under development. Therefore authors propose the trigger mode which combines functionality of two existing modes. The proposed trigger, called Zero Suppression Trigger, is compatible with the existing interfaces of the PC software, but is also capable to verify and filter incoming signals and transfer only recognized events. The results of the implementation and simulation are presented.},
 type={Article},
 title={Zero-Suppression Trigger Mode for GEM Detector Measurement System},
 URL={http://www.czasopisma.pan.pl/Content/118871/PDF/14_3144_Kolasinski_sk1.pdf},
 doi={10.24425/ijet.2021.135950},
 keywords={FPGA, GEM, trigger, sequencer, DAQ, Xilinx},
}