The paper deals with a multiple fault diagnosis of DC transistor circuits with limited accessible terminals for measurements. An algorithm for identifying faulty elements and evaluating their parameters is proposed. The method belongs to the category of simulation before test methods. The dictionary is generated on the basis of the families of characteristics expressing voltages at test nodes in terms of circuit parameters. To build the fault dictionary the n-dimensional surfaces are approximated by means of section-wise piecewise-linear functions (SPLF). The faulty parameters are identified using the patterns stored in the fault dictionary, the measured voltages at the test nodes and simple computations. The approach is described in detail for a double and triple fault diagnosis. Two numerical examples illustrate the proposed method.

This paper presents a novel strategy of fault classification for the analog circuit under test (CUT). The proposed classification strategy is implemented with the one-against-one Support Vector Machines Classifier (SVC), which is improved by employing a fault dictionary to accelerate the testing procedure. In our investigations, the support vectors and other relevant parameters are obtained by training the standard binary support vector machines. In addition, a technique of radial-basis-function (RBF) kernel parameter evaluation and selection is invented. This technique can find a good and proper kernel parameter for the SVC prior to the machine learning. Two typical analog circuits are demonstrated to validate the effectiveness of the proposed method.