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Abstract

We present two main ways to precisely create the equivalent transfer function of picosecond time-to-digital converters based on commonly used method with tapped time coding delay lines. The ways consist either in evaluation of the quantization steps boundaries of the delay lines or in summation of numbers of the line quantization steps. The paper contains results of comprehensive analysis of both methods. The advantage and high versatility of the addition method is demonstrated.
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Bibliography

[1] Szplet, R., Jachna, Z., Kwiatkowski, P.,&Rózyc K. (2013). A 2.9 ps equivalent resolution interpolating time counter based on multiple independent coding lines. Measurement Science and Technology, 20(3), 1–15. https://doi.org/10.1088/0957-0233/26/7/075002
[2] Wu, J., & Shi, Z. (2008). The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay. Proceedings of the IEEE Nuclear Science Symposium Conference Record, Dresden. 3440–3446. https://lss.fnal.gov/archive/2008/conf/fermilab-conf-08-498-e.pdf
[3] Szplet, R. (2014). Time-to-digital converters. In Carbone P., Kiaei, S., & Xu, W. (Eds.). Design, Modeling and Testing of Data Converters (pp. 211–246). Springer-Verlag. https://doi.org/10.1007/ 978-3-642-39655-7_7
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[7] Rivoir J. (2006). Statistical Linearity Calibration of Time-to-Digital Converters Using a Free- Running Ring Oscillator. Proceedings of the 15th Asian Test Symposium, Fukuoka, Japan. 45–50. https://doi.org/10.1109/ATS.2006.260991
[8] Chaberski, D., Frankowski, R., Gurski, M., & Zielinski, M. (2017). Comparison of interpolators used for time-interval measurement systems based on multiple-tapped delay line. Metrology and Measurement Systems, 24(2), 401–412.
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[11] Xie, W., Chen, H., & Li, D. D. U. (2021). Efficient time-to-digital converters in 20 nm FPGAs with wave union. IEEE Transactions on Industrial Electronics (Early Access). https://doi.org/10.1109/ TIE.2021.3053905
[12] Frankowski, R., Gurski, M., & Płóciennik, P. (2016). Optical methods of the delay cells characteristics measurements and their applications. Optical and Quantum Electronics, 48, 188. https://doi.org/10.1007/s11082-016-0465-6
[13] Kalisz, J., Orzanowski, T., & Szplet, R. (2000). Delay-locked loop technique for temperature stabilisation of internal delays of CMOS FPGA devices. Electronics Letters, 36(14), 1184–1185.
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Authors and Affiliations

Dominik Sondej
1
Rafał Szymanowski
1
Ryszard Szplet
1

  1. Military University of Technology, Faculty of Electronics, Institute of Communication Systems, gen. S. Kaliskiego 2, 00-908 Warsaw 46, Poland

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