In this work we report simulation and experimental results for an MWIR HgCdTe photodetector designed by computer simulation and fabricated in a joint laboratory run by VIGO Sytems S.A. and Military University of Technology. The device is based on a modified N+pP+ heterostructure grown on 2”., epiready, semi-insulating (100) GaAs substrates in a horizontal MOCVD AIX 200 reactor.

The devices were examined by measurements of spectral and time responses as a function of a bias voltage and operating temperatures. The time response was measured with an Optical Parametric Oscillator (OPO) as the source of ~25 ps pulses of infrared radiation, tuneable in a 1.55–16 μm spectral range. Two-stage Peltier cooled devices (230 K) with a 4.1 μm cut-off wavelength were characterized by 1.6 × 1012 cm Hz1/2/W peak detectivity and < 1 ns time constant for V > 500 mV.

Decisions involving comparisons of Arabic number digits often exhibit an interference between the physical size of the digit and the implied numerical magnitude, a phenomenon called the size-congruity effect. Related research over the past four decades has yielded two competing models of the phenomenon: an early interaction account, where interference between numerical and physical magnitude occurs at an early encoding stage, and a late interaction account, where the interference occurs downstream as response competition during the decision process. In the present study, we asked participants to compare the physical sizes of pairs of Arabic digits. We fit the resulting response time distributions with a shifted Wald model, a single boundary accumulator model, which gave us estimates of information accumulation rate (drift rate), response threshold, and nondecision time. We found that incongruity between physical size and numerical magnitude affected the decision-related estimates of drift rate and response threshold. Further, a Bayesian analysis confirmed a null effect of congruity on nondecision time. These results indicate that the observed interference originates from decision-related processes, lending further support for a late interaction account of the size-congruity effect.

The paper reports on a long-wave infrared (cut-off wavelength ~ 9 μm) HgCdTe detector operating under nbiased condition and room temperature (300 K) for both short response time and high detectivity operation. The ptimal structure in terms of the response time and detectivity versus device architecture was shown. The response time of the long-wave (active layer Cd composition, xCd = 0.19) HgCdTe detector for 300 K was calculated at a level of τs ~ 1 ns for zero bias condition, while the detectivity − at a level of D* ~ 109 cmHz1/2/W assuming immersion. It was presented that parameters of the active layer and P+ barrier layer play a critical role in order to reach τs ≤ 1 ns. An extra series resistance related to the processing (RS+ in a range 5−10 Ω) increased the response time more than two times (τs ~ 2.3 ns).

From the perspective of a virtual power plant (VPP) with electric vehicles (EVs), a self-scheduling strategy considering the response time margin (RTM) and state of charge margin (SOCM) is proposed. Firstly, considering the response state of the state of charge (SOC) and charge-discharge state of EVs, a VPP based response capacity determination model of EVs is established. Then, RTM and SOCM indexes are introduced on the basis of the power system scheduling target and the EV users’ traveling demands. The RTM and SOCM indices are calculated and then are used to generate a priority sequence of responsive EVs for the VPP. In the process of the scheduling period and rolling iteration, the scheduling schemes of the EVs in the VPP for multiple time periods are determined. Finally, the VPP self-scheduling strategy is validated by taking an VPP containing three kinds of EV users as an example. Simulation results show that with the proposed strategy, the VPP is able to respond to the scheduling power from the power system, while ensuring the traveling demands of the EV users at the same time.

The dual core bit-byte CPU must be equipped with properly designed circuits, providing interface between the two processor units, and making it possible to exploit all its advantages like versatility of the byte unit and speed of the bit unit. First of all, the interface circuits should be designed in such a way, that they don’t disturb maximally parallel operation of the units, and that the CPU as a whole works in the same manner as in a standard PLC. The paper presents hardware solutions supporting effective operation of PLC CPU-s. Possibilities of solving problems concerning data exchange between a CPU and peripheral circuits were presented, with a special stress on timers and counters, and also on data exchange between the bit unit and the byte unit. The objective of the proposed solutions is to decrease the time necessary for a CPU to access its peripheries.