Search results

Filters

  • Journals
  • Authors
  • Keywords
  • Date
  • Type

Search results

Number of results: 37
items per page: 25 50 75
Sort by:
Download PDF Download RIS Download Bibtex

Abstract

This article presents the simulation of a BLDC motor and its closed control system in FPGA. The simulation is based on a mathematical model of the motor, including the electromagnetic torque, phase currents, back electromotive force, etc. In order to ensure calculation precision, the equations describing the motor were solved using a floating point representation of real numbers, and a small step of numerical calculations of 1 μs was assumed. The time step selection methodology has been discussed in detail. The motor model was executed with the use of Textual Programming Languages (with HDL codes).

Go to article

Authors and Affiliations

Marcin Baszyński
Download PDF Download RIS Download Bibtex

Abstract

The paper presents modification of the method dedicated to a complex area decomposition of a set of logic functions whereas the

altered method is dedicated to implement the considered logic circuits within FPGA structures. The authors attempted to reach solutions where the number of configurable logic blocks and the number of structural layer would be reasonably balanced on the basis of the minimization principle. The main advantage of the procedure when the decomposition is carried out directly on the BDD diagram is the opportunity of immediate checking whether the decomposed areas of the diagram do not exceed the resources of logic blocks incorporated into the integrated circuits that are used for implementation of the logic functions involved.

Go to article

Authors and Affiliations

A. Dzikowski
E. Hrynkiewicz
Download PDF Download RIS Download Bibtex

Abstract

Analog-to-Digital Converters (ADCs) are devices that transform analog signals into digital signals and are used in various applications such as audio recording, data acquisition, and measurement systems [1]. Prior to the development of actual chip, there is a need for prototyping, testing and verifying the performance of ADCs in different scenarios. Analog macros cannot be tested on an FPGA. In order to ensure the macros function properly, the emulation of the ADC is done first. This is a digital module and can be designed in System Verilog. This paper demonstrates the design of the module on FPGA for Analog to Digital Converter (ADC) emulation. The emulation is done specific to the ADC macro which has programmable resolutions of 12/10/8/6 bit.
Go to article

Authors and Affiliations

Huma Tabassum
1
Krishna Prathik BV
1
Sujatha S Hiremath
1

  1. RV College of Engineering, India
Download PDF Download RIS Download Bibtex

Abstract

In modern digital world, there is a strong demand for efficient data streams processing methods. One of application areas is cybersecurity — IPsec is a suite of protocols that adds security to communication at the IP level. This paper presents principles of high-performance FPGA architecture for data streams processing on example of IPsec gateway implementation. Efficiency of the proposed solution allows to use it in networks with data rates of several Gbit/s.
Go to article

Authors and Affiliations

Mateusz Korona
Krzysztof Skowron
Mateusz Trzepiński
Mariusz Rawski
Download PDF Download RIS Download Bibtex

Abstract

In this article, an analysis of an innovative system for filtering signals in the audible range (16 Hz - 20 kHz) on programmable logic devices using a filters with a finite impulse response, is presented. Mentioned system was neat combination of software and hardware platform, where in the program layer a multiple programming languages including VHDL, JavaScript, Matlab or HTML were used to create completely useful application. To determine the coefficients of polynomial filters the Matlab Filter Design & Analysis Tool was used. Thanks to the developed graphic layer, a user-friendly interface was created, which allows easily transfer the required coefficients from the computer to the executive system. The practical implementation made on the FPGA platform, specifically on the Altera DE2- 115 development kit with the FPGA Cyclone IV, was compared with simulation realization of Matlab FIR filters. The performed research confirm the effectiveness of filtration in real time with up to 128th order of the filter for both audio channels simultaneously in FPGA-based system.
Go to article

Authors and Affiliations

Adrian Lipowski
1
Paweł Majewski
1
Sławomir Pluta
1

  1. Opole University Technology, Opole, Poland
Download PDF Download RIS Download Bibtex

Abstract

A novel approach to a trigger mode in the Gas Electron Multiplier (GEM) detector readout system is presented. The system is already installed at WEST tokamak. The article briefly describes the architecture of the GEM detector and the measurement system. Currently the system can work in two trigger modes: Global Trigger and Local Trigger. All trigger processing blocks are parts of the Charge Signal Sequencer module which is responsible for transferring data to the PC. Therefore, the article presents structure of the Sequencer with details about basic blocks, theirs functionality and output data configuration. The Sequencer with the trigger algorithms is implemented in an FPGA chip from Xilinx. Global Trigger, which is a default mode for the system, is not efficient and has limitations due to storing much data without any information. Local trigger which is under tests, removes data redundancy and is constructed to send only valid data, but the rest of the software, especially on the PC side, is still under development. Therefore authors propose the trigger mode which combines functionality of two existing modes. The proposed trigger, called Zero Suppression Trigger, is compatible with the existing interfaces of the PC software, but is also capable to verify and filter incoming signals and transfer only recognized events. The results of the implementation and simulation are presented.
Go to article

Authors and Affiliations

Piotr Kolasinski
1
Krzysztof Pozniak
1
Andrzej Wojenski
1
Paweł Linczuk
2
Rafał Krawczyk
1 3
Michał Gaska
1
Wojciech Zabolotny
1
Grzegorz Kasprowicz
1
Maryna Chernyshova
4
Tomasz Czarski
4

  1. Institute of Electronic Systems, Faculty of Electronics and Information Technology, University of Technology, Warsaw, Poland
  2. Institute of Electronic Systems, Faculty of Electronics and Information Technology, University of Technology, Warsaw, Poland
  3. CERN, Geneva, Switzerland
  4. Institute of Plasma Physics and Laser Microfusion, Warsaw, Poland
Download PDF Download RIS Download Bibtex

Abstract

In this article, a monitoring system based on IoT technologies of the substation electrical system in the Republic of Kazakhstan was developed. At the moment, the operation of power systems is extremely important to maintain the frequency of electric current over time. For management and monitoring applications, it is necessary to take into account communication within acceptable limits. IoT technologies are considered the main functions in applications for monitoring and managing energy systems in real time, as well as making effective decisions on both technical and financial issues of the system, for monitoring the main form of data registration on an electric power substation in the city of Shymkent of the Republic of Kazakhstan, for consistent effective decision-making by system operators. In this work, an Internet of Things-based monitoring system was implemented and implemented for the substation of the power system using a specialized device built into the FPGA controller for fast integrated digitalization of transformer substations of real-time distribution electrical networks. The IoT platform also provides complete remote observability and will increase reliability for power system operators in real time. This article is mainly aimed at providing a practical application that has been implemented and tested.
Go to article

Authors and Affiliations

Maksat Kalimoldayev
1
Waldemar Wójcik
2
Zhazira Shermantayeva
1

  1. Institute ofInformation and Computing Technologies of the KN of the Ministry ofInternal Affairs of the Republic of Kazakhstan
  2. Lublin University of Technology, Lublin, Poland
Download PDF Download RIS Download Bibtex

Abstract

The cold start of the space GPS receiver, i.e. the start without any information about the receiver position, satellite constellation, and time, is complicated by a large Doppler shift of a navigation signal caused by the satellite movement on the Earth orbit. That increases about five times the search space of the navigation signals compared to the standard GPS receiver. The paper investigates a method of the acceleration of the GPS receiver cold start time designed for the pico- and femto-satellites. The proposed method is based on a combination of the parallel search in Doppler frequency and PRN codes and the serial search in code phase delay. It can shorten the cold start time of the GPS receiver operating on LEO orbit from about 300 to 60 seconds while keeping the simplicity of FPGA signal processor and low power consumption. The developed algorithm was successfully implemented and tested in the piNAV GPS receiver. The energy required for the obtaining of the position fix was reduced five times from 36 on to 7.7 Joules. This improvement enables applications of such receiver for the position determination in smaller satellites like Pocket Cube or femto-satellites with a lower energy budget than the Cube Satellite.

Go to article

Authors and Affiliations

Pavel Kovář
Download PDF Download RIS Download Bibtex

Abstract

The aim of the paper is to present the implementation of a PLC designed in the form of a System-on-a-Chip. The presented PLC is compatible with the IEC61131‒3 standard. More precisely, the Instruction List language is the native language of the designed CPU, so there is no need for multiple language transformations. In the proposed solution each instruction of the CPU program written in Instruction List is directly translated to machine code. The designed CPU is capable of performing logic operations up to 32-bit Boolean data types. However, the developed CPU is very flexible due to its architecture: data memory can be addressed as bit/byte/word/dword. Moreover, diverse blocks such as timers, counters, and hardware acceleration blocks, can be connected to the CPU by means of an APB AMBA bus. The designed PLC has been implemented in an FPGA device and can be used in cyber-physical systems and Industry 4.0.

Go to article

Authors and Affiliations

P. Mazur
R. Czerwinski
M. Chmiel
Download PDF Download RIS Download Bibtex

Abstract

Infrared detectors are usually characterized by 1/f noise when operating with biasing. This type of noise significantly reduces detection capabilities for low-level and slow signals. There are a few methods to reduce the influence of 1/f noise, like filtering or chopper stabilization with lock-in. Using the first one, a simple 1st-order analog low-pass filter built-in amplifier usually cuts off 1/f noise fluctuations at low frequencies. In comparison, the stabilization technique modulates the signal transposing to a higher frequency with no 1/f noise and then demodulates it back (lock-in amplifiers). However, the flexible tuned device, which can work precisely at low frequencies, is especially desirable in some applications, e.g., optical spectroscopy or interferometry. The paper describes a proof-of-concept of an IR detection module with an adjustable digital filter taking advantage of finite impulse response type. It is based on the high-resolution analog-to-digital converter, field-programmable gate array, and digital-to-analog converter. A microcontroller with an implemented user interface ensures control of such a prepared filtering path. The module is a separate component with the possibility of customization and can be used in experiments or applications in which the reduction of noises and unexpected interferences is needed.
Go to article

Authors and Affiliations

Krzysztof Achtenberg
1
ORCID: ORCID
Janusz Mikołajczyk
1
ORCID: ORCID
Zbigniew Bielecki
1
ORCID: ORCID

  1. Institute of Optoelectronics, Military University of Technology, Warsaw, Poland
Download PDF Download RIS Download Bibtex

Abstract

Modern electronics systems consist of not only with the power electronics converters, but also with the friendly user interface which allow you to read the operating parameters and change them. The simplest solution of the user interface is to use alphanumeric display which displays information about the state of the converter. With a few additional buttons you can change the settings. This solution is simple, inexpensive but allows only local control (within walking distance from the system) and the number of displayed information is low. You can create extensive menu, but it causes problems with access to information. This paper presents the example of a rotating energy storage universal solution which is lack of the above mentioned disadvantages.
Go to article

Authors and Affiliations

Marcin Baszyński
Tomasz Siostrzonek
Download PDF Download RIS Download Bibtex

Abstract

Mitigation of electromagnetic inference (EMI) is currently a challenge for scientists and designers in order to cope with electromagnetic compatibility (EMC) compliance in switching mode power supply (SMPS) and ensure the reliability of the whole system. Standard filtering techniques: passive and active ones present some insufficiency in terms of performance at high frequencies (HF) because analog components would no longer be controllable and this is mainly due to their parasitic elements. So developing EMI digital filters is very interesting, especially with the embedment of a machine control system on a field programmable gate array (FPGA) chip. In this paper, we present a design of an active digital EMI filter (ADF) to be integrated in a drive train system of an electric vehicle (EV). Hardware design as well as FPGA implementation issues have been presented to prove the efficiency of the developed digital filtering structure.

Go to article

Authors and Affiliations

Yosr Bchir
Soufien Gdaim
Hamza Djilali
Abdellatif Mtibaa
Download PDF Download RIS Download Bibtex

Abstract

Department of Electrical Drive and Industrial Equipment University of Science and Technology (AGH) The article describes the method of determining mechanical losses and electromagnetic motor torque on the example of a flywheel energy storage system utilizing BLDC motor. The description of the test stand contains: the topology of power factor correction boost rectifier, an inverter supplying the BLDC motor, and the measuring system. The detailed experimental results are included in the paper.

Go to article

Authors and Affiliations

Stanisław Piróg
Marcin Baszyński
Download PDF Download RIS Download Bibtex

Abstract

The designing process of high resolution time interval measurement systems creates many problems that need to be eliminated. The problems are: the latch error, the nonlinearity conversion, the different duty cycle coefficient of the clock signal, and the clock signal jitter. Factors listed above affect the result of measurement. The FPGA (Field Programmable Gate Array) structure also imposes some restrictions, especially when a tapped delay line is constructed. The article describes the high resolution time-to-digital converter, implemented in a FPGA structure, and the types of errors that appear there. The method of minimization and processing of data to reduce the influence of errors on the measurement is also described.

Go to article

Authors and Affiliations

Stanisław Grzelak
Marcin Kowalski
Jarosław Czoków
Marek Zieliński
Download PDF Download RIS Download Bibtex

Abstract

This paper describes the arithmetic blocks based on Montgomery Multiplier (MM), which reduces complexity, gives lower power dissipation and higher operating frequency. The main objective in designing these arithmetic blocks is to use modified full adder structure and carry save adder structure that can be implemented in algorithm based MM circuit. The conventional full adder design acts as a benchmark for comparison, the second is the modified Boolean equation for full adder and third design is the design of full adder consisting of two XOR gate and a 2-to-1 Multiplexer. Besides Universal gates such as NOR gate and NAND gate, full adder circuits are used to further improve the speed of the circuit. The MM circuit is evaluated based on different parameters such as operating frequency, power dissipation and area of occupancy in FPGA board. The schematic designs of the arithmetic components along with the MM architecture are constructed using Quartus II tool, while the simulation is done using Model sim for verification of circuit functionality which has shown improvement on the full adder design with two XOR gate and one 2-to-1 Multiplexer implementation in terms of power dissipation, operating frequency and area.

Go to article

Authors and Affiliations

P. Velrajkumar
C. Senthilpari
J. Sheela Francisca
T. Nirmal Raj
Download PDF Download RIS Download Bibtex

Abstract

The paper presents a solution of the control system for fatigue test stand MZGS-100 PL, comprising the integrated Real-Time controller based on FPGA (Field-Programmable Gate Array) technology with LabVIEW software. The described control system performs functions such as continuous regulation of speed induction motor, measuring strain of the lever machine and the test specimen, displacement of the polyharmonic vibrator, as well as the elimination of interferences, overload protection and emergency stop of the machine. The fatigue test stand also allows to set the pseudo-random history of energy parameter W(t).

Go to article

Bibliography

[1] A. Valera-Medina, A. Giles, D. Pugh, S. Morris, M. Pohl, and A. Ortwein. Investigation of combustion of emulated biogas in a gas turbine test rig. Journal of Thermal Science, 27:331–340, 2018. doi: 10.1007/s11630-018-1024-1.
[2] K. Tanaka and I. Ushiyama. Thermodynamic performance analysis of gas turbine power plants with intercooler: 1st report, Theory of intercooling and performance of intercooling type gas turbine. Bulletin of JSME, 13(64):1210–1231, 1970. doi: 10.1299/jsme1958.13.1210.
[3] H.M. Kwon, T.S. Kim, J.L. Sohn, and D.W. Kang. Performance improvement of gas turbine combined cycle power plant by dual cooling of the inlet air and turbine coolant using an absorption chiller. Energy, 163:1050–1061, 2018. doi: 10.1016/j.energy.2018.08.191.
[4] A.T. Baheta and S.I.-U.-H. Gilani. The effect of ambient temperature on a gas turbine performance in part load operation. AIP Conference Proceedings, 1440:889–893, 2012. doi: 10.1063/1.4704300.
[5] F.R. Pance Arrieta and E.E. Silva Lora. Influence of ambient temperature on combined-cycle power-plant performance. Applied Energy, 80(3):261–272, 2005. doi: 10.1016/j.apenergy.2004.04.007.
[6] M. Ameri and P. Ahmadi. The study of ambient temperature effects on exergy losses of a heat recovery steam generator. In: Cen, K., Chi, Y., Wang, F. (eds) Challenges of Power Engineering and Environment. Springer, Berlin, Heidelberg, 2007. doi: 10.1007/978-3-540-76694-0_9.
[7] M.A.A. Alfellag: Parametric investigation of a modified gas turbine power plant. Thermal Science and Engineering Progress, 3:141–149, 2017. doi: 10.1016/j.tsep.2017.07.004.
[8] J.H. Horlock and W.A. Woods. Determination of the optimum performance of gas turbines. Proceedings of the Institution of Mechanical Engineers, Part C: Journal of Mechanical Engineering Science, 214:243–255, 2000. doi: 10.1243/0954406001522930.
[9] L. Battisti, R. Fedrizzi, and G. Cerri. Novel technology for gas turbine blade effusion cooling. In: Proceedings of the ASME Turbo Expo 2006: Power for Land, Sea, and Air. Volume 3: Heat Transfer, Parts A and B. pages 491–501. Barcelona, Spain. May 8–11, 2006. doi: 10.1115/GT2006-90516.
[10] F.J. Wang and J.S. Chiou. Integration of steam injection and inlet air cooling for a gas turbine generation system. Energy Conversion and Management, 45(1):15–26, 2004. doi: 10.1016/S0196-8904 (03)00125-0.
[11] Z. Wang. 1.23 Energy and air pollution. In I. Dincer (ed.): Comprehensive Energy Systems, pp. 909–949. Elsevier, 2018. doi: 10.1016/B978-0-12-809597-3.00127-9.
[12] Z. Khorshidi, N.H. Florin, M.T. Ho, and D.E. Wiley. Techno-economic evaluation of co-firing biomass gas with natural gas in existing NGCC plants with and without CO$_2$ capture. International Journal of Greenhouse Gas Control, 49:343–363, 2016. doi: 10.1016/j.ijggc.2016.03.007.
[13] K. Mohammadi, M. Saghafifar, and J.G. McGowan. Thermo-economic evaluation of modifications to a gas power plant with an air bottoming combined cycle. Energy Conversion and Management, 172:619–644, 2018. doi: 10.1016/j.enconman.2018.07.038.
[14] S. Mohtaram, J. Lin, W. Chen, and M.A. Nikbakht. Evaluating the effect of ammonia-water dilution pressure and its density on thermodynamic performance of combined cycles by the energy-exergy analysis approach. Mechanika, 23(2):18110, 2017. doi: 10.5755/j01.mech.23.2.18110.
[15] M. Maheshwari and O. Singh. Comparative evaluation of different combined cycle configurations having simple gas turbine, steam turbine and ammonia water turbine. Energy, 168:1217–1236, 2019. doi: 10.1016/j.energy.2018.12.008.
[16] A. Khaliq and S.C. Kaushik. Second-law based thermodynamic analysis of Brayton/Rankine combined power cycle with reheat. Applied Energy, 78(2):179–197, 2004. doi: 10.1016/j.apenergy.2003.08.002.
[17] M. Aliyu, A.B. AlQudaihi, S.A.M. Said, and M.A. Habib. Energy, exergy and parametric analysis of a combined cycle power plant. Thermal Science and Engineering Progress. 15:100450, 2020. doi: 10.1016/j.tsep.2019.100450.
[18] M.N. Khan, T.A. Alkanhal, J. Majdoubi, and I. Tlili. Performance enhancement of regenerative gas turbine: air bottoming combined cycle using bypass valve and heat exchanger—energy and exergy analysis. Journal of Thermal Analysis and Calorimetry. 144:821–834, 2021. doi: 10.1007/s10973-020-09550-w.
[19] F. Rueda Martínez, A. Rueda Martínez, A. Toleda Velazquez, P. Quinto Diez, G. Tolentino Eslava, and J. Abugaber Francis. Evaluation of the gas turbine inlet temperature with relation to the excess air. Energy and Power Engineering, 3(4):517–524, 2011. doi: 10.4236/epe.2011.34063.
[20] A.K. Mohapatra and R. Sanjay. Exergetic evaluation of gas-turbine based combined cycle system with vapor absorption inlet cooling. Applied Thermal Engineering, 136:431–443, 2018. doi: 10.1016/j.applthermaleng.2018.03.023.
[21] A.A. Alsairafi. Effects of ambient conditions on the thermodynamic performance of hybrid nuclear-combined cycle power plant. International Journal of Energy Research, 37(3):211–227, 2013. doi: 10.1002/er.1901.
[22] A.K. Tiwari, M.M. Hasan, and M. Islam. Effect of ambient temperature on the performance of a combined cycle power plant. Transactions of the Canadian Society for Mechanical Engineering, 37(4):1177–1188, 2013. doi: 10.1139/tcsme-2013-0099.
[23] T.K. Ibrahim, M.M. Rahman, and A.N. Abdalla. Gas turbine configuration for improving the performance of combined cycle power plant. Procedia Engineering, 15:4216–4223, 2011. doi: 10.1016/j.proeng.2011.08.791.
[24] M.N. Khan and I. Tlili. New advancement of high performance for a combined cycle power plant: Thermodynamic analysis. Case Studies in Thermal Engineering. 12:166–175, 2018. doi: 10.1016/j.csite.2018.04.001.
[25] S.Y. Ebaid and Q.Z. Al-hamdan. Thermodynamic analysis of different configurations of combined cycle power plants. Mechanical Engineering Research. 5(2):89–113, 2015. doi: 10.5539/mer.v5n2p89.
[26] R. Teflissi and A. Ataei. Effect of temperature and gas flow on the efficiency of an air bottoming cycle. Journal of Renewable and Sustainable Energy, 5(2):021409, 2013. doi: 10.1063/1.4798486.
[27] A.A. Bazmi, G. Zahedi, and H. Hashim. Design of decentralized biopower generation and distribution system for developing countries. Journal of Cleaner Production, 86:209–220, 2015. doi: 10.1016/j.jclepro.2014.08.084.
[28] A.I. Chatzimouratidis and P.A. Pilavachi. Decision support systems for power plants impact on the living standard. Energy Conversion and Management, 64:182–198, 2012. doi: 10.1016/j.enconman.2012.05.006.
[29] T.K. Ibrahim, F. Basrawi, O.I. Awad, A.N. Abdullah, G. Najafi, R. Mamat, and F.Y. Hagos. Thermal performance of gas turbine power plant based on exergy analysis. Applied Thermal Engineering, 115:977–985, 2017. doi: 10.1016/j.applthermaleng.2017.01.032.
[30] M. Ghazikhani, I. Khazaee, and E. Abdekhodaie. Exergy analysis of gas turbine with air bottoming cycle. Energy, 72:599–607, 2014. doi: 10.1016/j.energy.2014.05.085.
[31] M.N. Khan, I. Tlili, and W.A. Khan. thermodynamic optimization of new combined gas/steam power cycles with HRSG and heat exchanger. Arabian Journal for Science and Engineering, 42:4547–4558, 2017. doi: 10.1007/s13369-017-2549-4.
[32] N. Abdelhafidi, İ.H. Yılmaz, and N.E.I. Bachari. An innovative dynamic model for an integrated solar combined cycle power plant under off-design conditions. Energy Conversion and Management, 220:113066, 2020. doi: 10.1016/j.enconman.2020.113066.
[33] T.K. Ibrahim, M.K. Mohammed, O.I. Awad, M.M. Rahman, G. Najafi, F. Basrawi, A.N. Abd Alla, and R. Mamat. The optimum performance of the combined cycle power plant: A comprehensive review. Renewable and Sustainable Energy Reviews, 79:459–474, 2017. doi: 10.1016/j.rser.2017.05.060.
[34] M.N. Khan. Energy and exergy analyses of regenerative gas turbine air-bottoming combined cycle: optimum performance. Arabian Journal for Science and Engineering, 45:5895–5905, 2020. doi: 10.1007/s13369-020-04600-9.
[35] A.M. Alklaibi, M.N. Khan, and W.A. Khan. Thermodynamic analysis of gas turbine with air bottoming cycle. Energy, 107:603–611, 2016. doi: 10.1016/j.energy.2016.04.055.
[36] M. Ghazikhani, M. Passandideh-Fard, and M. Mousavi. Two new high-performance cycles for gas turbine with air bottoming. Energy, 36(1):294–304, 2011. doi: 10.1016/j.energy.2010.10.040.
[37] M.N. Khan and I. Tlili. Innovative thermodynamic parametric investigation of gas and steam bottoming cycles with heat exchanger and heat recovery steam generator: Energy and exergy analysis. Energy Reports, 4:497–506, 2018. doi: 10.1016/j.egyr.2018.07.007.
[38] M.N. Khan and I. Tlili. Performance enhancement of a combined cycle using heat exchanger bypass control: A thermodynamic investigation. Journal of Cleaner Production, 192:443–452, 2018. doi: 10.1016/j.jclepro.2018.04.272.
[39] M. Korobitsyn. Industrial applications of the air bottoming cycle. Energy Conversion and Management, 43(9-12):1311–1322, 2002. doi: 10.1016/S0196-8904(02)00017-1.
[40] T.K. Ibrahim and M.M. Rahman. optimum performance improvements of the combined cycle based on an intercooler–reheated gas turbine. Journal of Energy Resources Technology, 137(6):061601, 2015. doi: 10.1115/1.4030447.
Go to article

Authors and Affiliations

Wojciech Macek
Ewald Macha

Download PDF Download RIS Download Bibtex

Abstract

This paper presents low-cost, configurable PCI Express (PCIe) direct memory access (DMA) interface for implementation on Intel Cyclone V FPGAs. The DMA engine was designed to support DAQ tasks including pre-triggering acquisition for transient analysis and multichannel transmission. Performance of the interface has been evaluated on Terasic OVSK board (PCIe Gen2 x4). Target configuration of this interface is based on the Avalon-MM Hard IP for Cyclone V PCIe core and Jungo WinDriver x64 for Windows. A sample speed of 1200 MB/s has been reported for DMA writes to PCIe memory.
Go to article

Bibliography

[1] PCI Express Base Specification, rev. 3.0, PCI-SIG, Nov. 2010
[2] A. Wójcik, R. Łukaszewski, R. Kowalik, W. Winiecki, “Nonintrusive Appliance Load Monitoring: An Overview, Laboratory Test Results and Research Directions”, Sensors, 2019, 19, 3621
[3] A. Wójcik, P. Bilski, R. Łukaszewski, K. Dowalla, R. Kowalik, “Identification of the State of Electrical Appliances with the Use of a Pulse Signal Generator”, Energies, 2021, 14, 673.
[4] K. N. Trung, E. Dekneuvel, B. Nicolle, O. Zammit, C. N. Van, G. Jacquemod, “Using FPGA for Real Time Power Monitoring in a NIALM System”, In Proc. 2013 IEEE International Symposium on Industrial Electronics (ISIE), 2013, pp. 1-6
[5] Intel Corporation, Modular Scatter-Gather DMA Core, In Embedded Peripherals IP User Guide v. 18.1
[6] Intel Corporation, Intel® Quartus® Prime Standard Edition User Guide v. 18.1, Platform Designer
[7] Intel Corporation, Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe Solutions User Guide, UG-01110, 2020
[8] Intel Corporation,V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide, UG-01154, 2016
[9] WinDriver, https://www.jungo.com/st/products/windriver/wd_windows/
[10] OpenVINO Stater Kit GT Edition User Manual, available on https://www.terasic.com.tw/
[11] L. Rota, M. Caselle, S. Chilingaryan, A. Kopmann, M. Weber, “A PCIe DMA Architecture for Multi-Gigabyte Per Second Data Transmission”, IEEE Transactions on Nuclear Science, vol. 62, no. 3, 2015, pp. 972 - 976
[12] A. Byszuk, J. Kołodziejski, G. Kasprowicz, K. Późniak, W. M. Zabołotny “Implementation of PCI Express bus communication for FPGA-based data acquisition systems”, In Proceedings of SPIE Vol. 8454, 2015
[13] L. Boyang, “Research and Implementation of XDMA High Speed Data Transmission IP Core Based on PCI Express and FPGA”, in 2019 IEEE 1st International Conference on Civil Aviation Safety and Information Technology (ICCASIT), Oct. 2019, pp. 408–411
Go to article

Authors and Affiliations

Krzysztof Mroczek
1

  1. Institute of Radioelectronics and Multimedia Technology, Warsaw University of Technology, Poland
Download PDF Download RIS Download Bibtex

Abstract

In the past it was usual to exert a huge effort in the design, simulation, and the real time implementation of the complicated electronic and communication systems, like GNSS receivers. The complexity of the system algorithms combined with the complexity of the available tools created a system that is difficult to track down for debugging or for redesign. So, the simulation and educational tools was different from the prototyping tools. In this paper the parallel search acquisition phase of a GPS receiver was simulated and implemented on FPGA using the same platform and through a graphical programming language. So this paper introduces the fruit of integrating the prototyping tools with the simulation tools as a single platform through which the complicated electronic systems can be simulated and prototyped.

Go to article

Authors and Affiliations

Mohamed Ibrahiem El Hawary
Gihan Gomah Hamza
Abdelhalim Zekry
Ibrahiem Mohamed Motawie
Download PDF Download RIS Download Bibtex

Abstract

The Sinara hardware platform is a modular, opensource measurement and control system dedicated to quantum applications that require hard real-time performance. The hardware is controlled and managed by the ARTIQ, open-source software that provides nanosecond timing resolution and submicrosecond latency. The Sampler is a general-purpose precision ADC sampling unit with programmable gain and configurable interface. It is used in numerous applications like laser frequency and intensity servo. This paper presents the Sampler module construction and obtained characteristics.
Go to article

Authors and Affiliations

Grzegorz Kasprowicz
1
Thomas Harty
2
Sébastien Bourdeauducq
3
Robert Jördens
4
David Allcock
5
Daniel Slichter
6
David Nadlinger
2
Joseph W. Britton
7 8
Ana Sotirova
2

  1. Warsaw University of Technology, Poland
  2. Oxford University, United Kingdom
  3. M-Labs, Hong Kong
  4. QUARTIQ, Germany
  5. Oregon University, United States
  6. National Institute of Standards and Technology (NIST), United States
  7. University of Maryland, United States
  8. Army Research Lab, United States
Download PDF Download RIS Download Bibtex

Abstract

Very often, a digital system includes sequential blocks which can be represented using a model of the finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and consumed energy. The paper proposes a novel technology-dependant design method targeting LUT-based Mealy FSMs. It belongs to the group of structural decomposition methods. The method is based on encoding the product terms of Boolean functions representing the FSM circuit. To diminish the number of LUTs, a partition of the set of internal states is constructed. It leads to three-level logic circuits of Mealy FSMs. Each function from the first level requires only a single LUT to be implemented. The method of constructing the partition with the minimum amount of classes is proposed. There is given an example of FSM synthesis with the proposed method. The experiments with standard benchmarks were conducted. They show that the proposed method can improve such FSM characteristics as the number of used LUTs. This improvement is accompanied by a decrease in performance. A positive side effect of the proposed method is a reduction in power consumption compared with FSMs obtained with other design methods.
Go to article

Bibliography

  1.  J. Baillieul and T. Samad, Encyclopedia of Systems and Control, Springer, 2015.
  2.  M. Arora, Embedded System Design, Introduction to SoC System Architecture, Learning Bytes Publishing, 2016.
  3.  V. Chakravarthi, A Practical Approach to VLSI System on Chip (SoC) Design, A Comprehensive Guide, Springer, 2020.
  4.  P. Minns and I. Elliot, FSM-based digital design using Verilog HDL, John Wiley and Sons, 2008.
  5.  S. Baranov, Logic and System Design of Digital Systems, Tallinn: TUT Press, 2008.
  6.  B.D. Brown and H.C. Card, “Stochastic neural computation. I computational elements”, IEEE Trans. Comput. 50(9), 891‒905 (2001).
  7.  O. Barkalov, L. Titarenko, and M. Mazurkiewicz, Foundations of Embedded Systems, Springer, 2019.
  8.  A. Ardakani, F. Leduc-Primeau, N. Onizawa, T. Hanyu, and W.J. Gross, “VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(10), 26882699 (2017).
  9.  P. Li, D.J. Lilja, W. Qian, M.D. Riedel, and K. Bazargan, “Logical computation on stochastic bit streams with linear finitestate machines”, IEEE Trans. Comput. 63(6), 1474‒1486 (2014).
  10.  Y. Xie, S. Liao, B. Yuan, Y. Wang, and Z. Wang, “Fully-parallel area-efficient deep neural network design using stochastic computing”, IEEE Trans. Circuits Syst. II-Express Briefs 64(12), 1382‒1386 (2017).
  11.  N. Das and P.A. Priya, “FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method”, Int. J. Reconfigurable Comput. 2018, 6831901 (2018).
  12.  J. Glaser, M. Damm, J. Haase, and C. Grimm, “TR-FSM: Transition-Based Reconfigurable Finite State Machine”, ACM Trans. Reconfigurable Technol. Syst. 4, 23:1‒23:14 (2011).
  13.  R. Czerwinski and D. Kania, Finite State Machine Logic Synthesis for Complex Programmable Logic Devices, Springer, 2013.
  14.  V. Sklyarov, I. Skliarova, A. Barkalov, and L. Titarenko, Synthesis and optimization of FPGA-based systems, Springer, 2014.
  15.  M. Kubica, D. Kania, and J. Kulisz, “A Technology Mapping of FSMs Based on a Graph of Excitations and Outputs”, IEEE Access 7, 16123‒16131 (2019).
  16.  A. Opara, M. Kubica, and D. Kania, “Methods of Improving Time Efficiency of Decomposition Dedicated at FPGA Structures and Using BDD in the Process of Cyber-Physical Synthesis”, IEEE Access 7, 20619‒20631 (2019).
  17.  M. Kubica and D. Kania, “Area-oriented technology mapping for LUT-based logic blocks”, Int. J. Appl. Math. Comput. Sci. 27(1), 207‒222 (2017).
  18.  M. Kubica, A. Opara, and D. Kania, “Logic Synthesis for FPGAs Based on Cutting of BDD”, Microprocess. Microsyst. 52, 173‒187 (2017).
  19.  I. Skliarova, V. Sklyarov, and A. Sudnitson, Design of FPGAbased circuits using Hierarchical Finite State Machines, Tallinn: TUT Press, 2012.
  20.  Altera, [Online]. http://www.altera.com (accesed: May, 2020).
  21.  Atmel, [Online]. http://www.atmel.com (accesed: May, 2020).
  22.  Xilinx, [Online]. http://www.xilinx.com (accesed: May, 2020).
  23.  I. Kuon, R. Tessier, and J. Rose, “FPGA architecture: Survey and Challenges”, Found. Trends Electron. Design Automat. 2(2), 135‒253 (2008).
  24.  I. Grout, Digital Systems Design with FPGAs and CPLDs, Elsevier Science, 2011.
  25.  S. Kilts, Advanced FPGA Design: Architecture, Implementation, and Optimization, Wiley-IEEE Press, 2007.
  26.  Intel, “Intel SoC FPGA Embedded Development Suite User Guide”. [Online]. https://www.intel.com/content/www/us/en/programmable/ documentation/lro1402536290550.html (accesed: May, 2020).
  27.  Xilinix, “Zynq UltraScale+MPSoC”. [Online]. https://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc. html#productTable (accesed: May, 2020).
  28.  G. Stringham, Hardware/firmware Interface Design: Best Practices for Improving Embedded Systems Development, Newnes, 2010.
  29.  I. Skliarova and V. Sklyarov, FPGA-BASED hardware accelerators, Springer, 2019.
  30.  T. Łuba, M. Rawski, and Z. Jachna, “Functional Decomposition as a universal method for logic synthesis of digital circuits”, in Proceedings of IX International Conference MIXDES’02, 2002, p. 285290.
  31.  A. Ling, D.P. Singh, and S.D. Brown, “FPGA technology mapping: a study of optimality”, in Proceedings 42nd Design Automation Conference (DAC05), 2005, pp. 427‒432.
  32.  M. Kubica and D. Kania, “Technology mapping oriented to adaptive logic modules”, Bull. Pol. Acad. Sci. Tech. Sci. 67(5), 947‒956 (2019).
  33.  O. Barkalov, L. Titarenko, K. Mielcarek, and S. Chmielewski, Logic Synthesis for FPGA-Based Control Units: Structural Decomposition in Logic Design, Springer, 2020.
  34.  S. Yang, “Logic Synthesis and Optimization Benchmarks User Guide”, tech. rep., Microelectronic Center of North Carolina, 1991.
  35.  G.D. Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.
  36.  E. Testa, L. Amaru, M. Soeken, A. Mishchenko, P. Vuillod, J. Luo, C. Casares, P. Gaillardon, and G.D. Micheli, “Scalable boolean methods in a modern synthesis flow”, in 2019 Design, Automation Test in Europe Conference Exhibition (DATE), 2019, pp. 1643‒1648.
  37.  R. Brayton and A. Mishchenko, “ABC: An Academic Industrial-Strength Verification Tool”, in Computer Aided Verification, pp. 24‒40 eds. T. Touili, B. Cook, and P. Jackson, Springer, 2010.
  38.  A. Opara, M. Kubica, and D. Kania, “Methods of Improving Time Efficiency of Decomposition Dedicated at FPGA Structures and Using BDD in the Process of Cyber-Physical Synthesis”, IEEE Access 7, 20619‒20631 (2019).
  39.  O. Barkalov, L. Titarenko, and K. Mielcarek, “Hardware reduction for LUT-based Mealy FSMs”, Int. J. Appl. Math. Comput. Sci. 28(3), 595‒607 (2018).
  40.  Xilinix, “Virtex-7 family overview”. [Online]. https://www.xilinx.com/products/silicon-devices/fpga/virtex-7.html (accesed: May, 2020).
  41.  A. Mishchenko, R.K. Brayton, J.H.R. Jiang, and S. Jang, “Scalable Don’t-Care-Based Logic Optimization and Resynthesis”, ACM Trans. Reconfigurable Technol. Syst. 4(4), 34(1‒23) (2011).
  42.  A. Mishchenko, S. Chatterjee, and R.K. Brayton, “Improve-ments to Technology Mapping for LUT-based FPGAs”, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2), 240253 (2007).
  43.  C. Scholl, Functional Decomposition with Application to FPGA Synthesis, Kluwer Academic Publishers, 2001.
  44.  L. Machado and J. Cortadella, “Support-Reducing Decomposition for FPGA Mapping”, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1), 213‒224 (2020).
  45.  R. Czerwinski, D. Kania, and J. Kulisz, “FSMs state encoding targeting at logic level minimization”, Bull. Pol. Acad. Sci. Tech. Sci. 54(4), 479‒487 (2006).
  46.  R. Czerwinski and D. Kania, “Synthesis method of high speed finite state machines”, Bull. Pol. Acad. Sci. Tech. Sci. 58(4), 635‒644 (2010).
  47.  A. Opara and D. Kania, “Decomposition-based logic synthesis for PAL-based CPLDs,” Int. J. Appl. Math. Comput. Sci. 20(2), 367‒384 (2010).
  48.  E. Sentowich, et al., “SIS: a system for sequential circuit synthesis”, in Proc. of the Inter. Conf. of Computer Design (ICCD’92), 1992, p.328333.
  49.  Xilinx, “XST User Guide. V. 11.3”. [Online]. http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/xst.pdf (accesed: May, 2020).
  50.  Vivado. [Online]. https://www.xilinx.com/products/design-tools/vivado.html (accesed: May, 2020).
  51.  A. Barkalov, L. Titarenko, M. Mazurkiewicz, and K. Krzywicki, “Encoding of terms in EMB-Based Mealy FSMs”, Appl. Sci. 10(8), 21 (2020).
  52.  S. Achasova, Synthesis algorithms for automata with PLAs, M: Soviet radio, 1987.
  53.  LGSynth93, “International Workshop on logic synthesis benchmark suite (LGSynth93)”. [Online]. https://people.engr.ncsu.edu/brglez/ CBL/benchmarks/LGSynth93/LGSynth93.tar, 1993 (accesed: February, 2018).
  54.  B. Lin, “Synthesis of multiple-level logic from symbolic highlevel description languages”, in IFIP International Conference on Very Large Scale Integration, 1989, pp. 187‒196).
  55.  M. Rawski, L. Jozwiak, M. Nowicka, and T. Łuba, “Nondisjoint decomposition of boolean functions and its application in FPGA-oriented technology mapping”, in EUROMICRO 97. Proceedings of the 23rd EUROMICRO Conference: New Frontiers of Information Technology (Cat. No.97TB100167), 1997, pp. 24‒30.
Go to article

Authors and Affiliations

Alexander Barkalov
1 2
ORCID: ORCID
Larysa Titarenko
1 3
ORCID: ORCID
Małgorzata Mazurkiewicz
1
ORCID: ORCID
Kazimierz Krzywicki
4
ORCID: ORCID

  1. University of Zielona Góra, ul. Licealna 9, 65-417 Zielona Góra, Poland
  2. Vasyl’ Stus Dohetsk National University, 21, 600-richya str., Vinytsia, 21021, Ukraine
  3. Kharkiv National University of Radio Electronics, Nauky avenye, 14, 6166, Kharkiv, Ukraine
  4. The Jacob of Paradies University, ul. Teatralna 25, 66-400 Gorzów Wielkopolski, Poland
Download PDF Download RIS Download Bibtex

Abstract

We present the implementation of the hardware ANS compressor in FPGAs. The main goal of the design was to propose a solution suitable to low-cost, low-energy embedded systems. We propose the streaming-rANS algorithm of the ANS family as a target for the implementation. Also, we propose a set of algorithm parameters that substantially reduce the use of FPGA resources, and we examine what is the influence of the chosen parameters on compression performance. Further, we compare our design to the lossless codecs found in literature, and to the streaming-rANS codecs with arbitrary parameters.
Go to article

Authors and Affiliations

Magdalena Pastuła
1
Paweł Russek
1
Kazimierz Wiatr
1

  1. AGH University of Krakow, Krakow, Poland
Download PDF Download RIS Download Bibtex

Abstract

The work presents a structural and functional model of a distributed low level radio frequency (LLRF) control, diagnostic and telemetric system for a large industrial object. An example of system implementation is the European TESLA-XFEL accelerator. The free electron laser is expected to work in the VUV region now and in the range of X-rays in the future. The design of a system based on the FPGA circuits and multi-gigabit optical network is discussed. The system design approach is fully parametric. The major emphasis is put on the methods of the functional and hardware concentration to use fully both: a very big transmission capacity of the optical fiber telemetric channels and very big processing power of the latest series of DSP/PC enhanced and optical I/O equipped, FPGA chips. The subject of the work is the design of a universal, laboratory module of the LLRF sub-system. The current parameters of the system model, under the design, are presented. The considerations are shown on the background of the system application in the hostile industrial environment. The work is a digest of a few development threads of the hybrid, optoelectronic, telemetric networks (HOTN). In particular, the outline of construction theory of HOTN node was presented as well as the technology of complex, modular, multilayer HOTN system PCBs. The PCBs contain critical sub-systems of the node and the network. The presented exemplary sub-systems are: fast optical data transmission of 2.5 Gbit/s, 3.125 Gbit/s and 10 Gbit/s; fast A/C and C/A multichannel data conversion managed by FPGA chip (40 MHz, 65 MHz, 105 MHz), data and functionality concentration, integration of floating point calculations in the DSP units of FPGA circuit, using now discrete and next integrated PC chip with embedded OS; optical distributed timing system of phase reference; and 1GbEth video interface (over UTP or FX) for CCD telemetry and monitoring. The data and functions concentration in the HOTN node is necessary to make efficient use of the multigigabit optical fiber transmission and increasing the processing power of the FPGA/DSP/PC chips with optical I/O interfaces. The experiences with the development of the new generation of HOTN node based on the new technologies of data and functions concentration are extremely promising, because such systems are less expensive and require less labour.

Go to article

Authors and Affiliations

R.S. Romaniuk
K.T. Poźniak
T. Czarski
K. Czuba
W. Giergusiewicz
G. Kasprowicz
W. Koprek

This page uses 'cookies'. Learn more