In this paper, the second-generation CMOS currentcontrolled- current-conveyor based on differential pair of operational transconductance amplifier has been researched and presented. Since the major improvement of its parasitic resistance at x-port can be linearly controlled by an input bias current, the proposed building block is then called “The Second-Generation Electronically-tunable Current-controlled Current Conveyor” (ECCCI). The applications are demonstrated in form of both 2 quadrant and 4 quadrant current-mode signal multiplier circuits. Characteristics of the proposed ECCCII and its application are simulated by the PSPICE program from which the results are proved to be in agreement with the theory.

In this paper, the usage of graphene transistors is introduced to be a suitable solution for extending low power designs. Static and current mode logic (CML) styles on both nanoscale graphene and silicon FINFET technologies are compared. Results show that power in CML styles approximately are independent of frequency and the graphene-based CML (GCML) designs are more power-efficient as the frequency and complexity increase. Compared to silicon-based CML (Si-CML) standard cells, there is 94% reduction in power consumption for G-CML counterparts. Furthermore, a G-CML 4-bit adder respectively offers 8.9 and 1.7 times less power and delay than the Si-CML adder.

Averaged models: an AC large signal, DC and AC small signals of a current-controlled buck converter are described. Only peak current mode control of a converter working in the continuous conduction mode (CCM) is considered. The model derivation differs from the typical approaches presented in the literature and doesn’t refer to the multi-loop concept of a current controlled converter. The separation of the variables method is used in the model derivation. The resulting models are presented in the form of an equation set and equivalent circuits. The calculations based on the presented models are verified by measurements and full-wave PSpice simulations.

Soft-switching technologies can effectively solve the problem of switching losses caused by increasing switching frequency of grid-connected inverters. As a branch of soft-switching technologies, load-side resonant soft-switching is a hotspot for applications of high-frequency inverters, because it has the advantage of achieving soft-switching without using additional components. However, the traditional PI control strategy based on the linear model is prone to destabilization and non-robust dynamic performance when large signal perturbation occurs. In this paper, a novel Passivity-Based Control (PBC) method is proposed to improve the dynamic performance of load-side resonant soft-switching grid-connected inverter. Besides, the model based on the Port Controlled Hamiltonian (PCH) model of the soft switching inverter is carried out, and the passivity-based controller is designed based on the established model using the way of interconnection and damping assignmentpassivity based control (IDA-PBC). Both stable performance and dynamic performance of the load-side resonant soft-switching inverter can be improved over the whole operating range. Finally, a 750 W load-side resonant soft-switching inverter simulation model is built and the output performance is compared with the traditional PI control strategy under stable and dynamic conditions. The simulation results show that the proposed control strategy reduces the harmonic distortion rate and improves the quality of the output waveforms.