Search results

Filters

  • Journals
  • Authors
  • Keywords
  • Date
  • Type

Search results

Number of results: 3
items per page: 25 50 75
Sort by:
Download PDF Download RIS Download Bibtex

Abstract

The dual core bit-byte CPU must be equipped with properly designed circuits, providing interface between the two processor units, and making it possible to exploit all its advantages like versatility of the byte unit and speed of the bit unit. First of all, the interface circuits should be designed in such a way, that they don’t disturb maximally parallel operation of the units, and that the CPU as a whole works in the same manner as in a standard PLC. The paper presents hardware solutions supporting effective operation of PLC CPU-s. Possibilities of solving problems concerning data exchange between a CPU and peripheral circuits were presented, with a special stress on timers and counters, and also on data exchange between the bit unit and the byte unit. The objective of the proposed solutions is to decrease the time necessary for a CPU to access its peripheries.

Go to article

Authors and Affiliations

M. Chmiel
Download PDF Download RIS Download Bibtex

Abstract

The aim of the paper is to present the implementation of a PLC designed in the form of a System-on-a-Chip. The presented PLC is compatible with the IEC61131‒3 standard. More precisely, the Instruction List language is the native language of the designed CPU, so there is no need for multiple language transformations. In the proposed solution each instruction of the CPU program written in Instruction List is directly translated to machine code. The designed CPU is capable of performing logic operations up to 32-bit Boolean data types. However, the developed CPU is very flexible due to its architecture: data memory can be addressed as bit/byte/word/dword. Moreover, diverse blocks such as timers, counters, and hardware acceleration blocks, can be connected to the CPU by means of an APB AMBA bus. The designed PLC has been implemented in an FPGA device and can be used in cyber-physical systems and Industry 4.0.

Go to article

Authors and Affiliations

P. Mazur
R. Czerwinski
M. Chmiel

This page uses 'cookies'. Learn more