Sound insulation of the finite double-panel structure (DPS) inserted with a cylindrical shell array is investigated by varying the sound incidence direction to improve its applicability. The effects of the vibro-acoustic characteristics of its constituents on the sound transmission loss (STL) are estimated in one-third octave bands from 20 Hz to 5 kHz for different incidence conditions. It shows that the first acoustic mode in the direction parallel to two panels (longitudinal modes) produces both the sudden variation of sound insulation with frequency and a large dependency on the incidence angle. Mineral wools are placed on two boundaries perpendicular to the panels, and the sound insulation is explored for different thicknesses of the porous materials. An absorbent layer with a certain thickness (more than 30 mm in our work) sufficiently eliminates the longitudinal mode, resulting in the improvement in the sound insulation by more than 15 dB and the decrease of its large variation with incidence direction. STLs with varying shell thicknesses are also assessed. It shows that the natural vibrations of the thin shells can give an enhancement in sound insulation by more than 10 dB in the frequency range of 1600–3700 Hz, corresponding to constructive interference.

In this work the construction of experimental setup for MEMS/NEMS deflection measurements is presented. The system is based on intensity fibre optic detector for linear displacement sensing. Furthermore the electronic devices: current source for driving the light source and photodetector with wide-band preamplifier are presented.

In this paper, the usage of graphene transistors is introduced to be a suitable solution for extending low power designs. Static and current mode logic (CML) styles on both nanoscale graphene and silicon FINFET technologies are compared. Results show that power in CML styles approximately are independent of frequency and the graphene-based CML (GCML) designs are more power-efficient as the frequency and complexity increase. Compared to silicon-based CML (Si-CML) standard cells, there is 94% reduction in power consumption for G-CML counterparts. Furthermore, a G-CML 4-bit adder respectively offers 8.9 and 1.7 times less power and delay than the Si-CML adder.