Details Details PDF BIBTEX RIS Title Low Power and Improved Speed Montgomery Multiplier using Universal Building Blocks Journal title International Journal of Electronics and Telecommunications Yearbook 2019 Volume vol. 65 Issue No 3 Authors Velrajkumar, P. ; Senthilpari, C. ; Sheela Francisca, J. ; Nirmal Raj, T. Keywords FPGA ; Model Sim ; Power dissipation ; speed ; Universal Logic Divisions of PAS Nauki Techniczne Coverage 477-483 Publisher Polish Academy of Sciences Committee of Electronics and Telecommunications Date 2019.09.06 Type Artykuły / Articles Identifier DOI: 10.24425/ijet.2019.129802 ; eISSN 2300-1933 (since 2013) ; ISSN 2081-8491 (until 2012) Source International Journal of Electronics and Telecommunications; 2019; vol. 65; No 3; 477-483 <div class="test"></div>