Details

Title

A New Approach of an Error Detecting and Correcting Circuit by Arithmetic Logic Blocks

Journal title

International Journal of Electronics and Telecommunications

Yearbook

2019

Volume

vol. 65

Issue

No 2

Authors

Keywords

EDAC ; ALU ; speed ; block reduction ; power ; slew rate

Divisions of PAS

Nauki Techniczne

Coverage

313-318

Publisher

Polish Academy of Sciences Committee of Electronics and Telecommunications

Date

2019.06.13

Type

Artykuły / Articles

Identifier

DOI: 10.24425/ijet.2019.126316 ; eISSN 2300-1933 (since 2013) ; ISSN 2081-8491 (until 2012)

Source

International Journal of Electronics and Telecommunications; 2019; vol. 65; No 2; 313-318
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