Title

A Modified Signal Feed-Through Pulsed Flip- Flop for Low Power Applications

Journal title

International Journal of Electronics and Telecommunications

Yearbook

2017

Volume

vol. 63

Issue

No 3

Authors

Panahifar, Ehsan ; Hassanzadeh, Alireza

Divisions of PAS

Nauki Techniczne

Publisher

Polish Academy of Sciences Committee of Electronics and Telecommunications

Date

2017

Identifier

DOI: 10.1515/eletel-2017-0032 ; eISSN 2300-1933 (since 2013) ; ISSN 2081-8491 (until 2012)

Source

International Journal of Electronics and Telecommunications; 2017; vol. 63; No 3

References

De Caro (2005), Petra novel high speed sense - amplifier - based flip - flop Very Large Scale Integr vol pp pp Nov, IEEE Trans VLSI Syst, 13. ; Khademzadeh (2005), Low power single - and double - edge - triggered flip - flops for high speed applications IEE Circuits Devices, Proc Syst, 20, 152. ; Klass (1998), Semi - dynamic and dynamic flip - flops with embedded logic in on Dig of pp, Symp VLSI Circuits Tech Papers, 108. ; Jin (2014), Fa Low Pulse - Triggered Flip - Flop Design Based on a Signal Feed - Through Transactions on Very Large Scale Integration, Power IEEE VLSI Systems, 15, 181. ; Darwish (2004), High - performance and low power conditional discharge flip - flop Very Large Scale Systems, IEEE Trans VLSI, 12, 477. ; David (2011), Money Weste CMOS Systems Perspective th ed, VLSI Design Circuits Education, 18. ; Amir (1999), new family of semi - dynamic and dynamic flip flops with embedded logic for high - performance processors Solid - State Circuits, IEEE, 34. ; Aleksic (2002), Conditional precharge techniques for power - efficient dual - edge clocking Low Design, Proc Int Symp Power Electron, 11, 56. ; Harris (2001), Skew Tolerant Circuit San CA, Design, 16. ; Burd (1996), Flow - through latch and edge - triggered flip - flop hybrid elements in Dig pp, IEEE Tech, 138. ; Nikolic (1999), Sense amplifier based flip flop Solid State Circuits Dig of pp Feb, Int Tech, 282. ; Lin (2012), Low power pulse triggered flip - flop design with conditional pulse enhancement scheme Very Large Scale pp Feb, IEEE Trans VLSI Syst, 14, 361. ; Narendra (2001), Comparative delay and energy of single edge - triggered and dual edge triggered pulsed flip - flops for high - performance microprocessors in, Proc, 207. ; Matsui (1994), MHz DCT macrocell using sense amplifying pipeline flip - flop scheme Solid - State Circuits, IEEE, 13, 200. ; Hamada (2006), Conditional data mapping flip - flops for low - power and highperformance systems Very Large Scale Systems, IEEE Trans VLSI, 13, 1379. ; Phyu (2005), low - power static dual edge triggered flip - flop using an output - controlled discharge configuration in, Proc IEEE Int Symp Circuits Syst, 19, 2429. ; Kawaguchi (1998), reduced clock swing flip flop for power reduction Solid State Circuits, IEEE, 1.