TY - JOUR N2 - Abstract Distributed arithmetic is well known technique of designing FIR filters in FPGA devices. The quality of such filter implementation strongly depends on synthesis results of the DALUT block. Heterogeneity of modern FPGA structures introduces new possibilities into implementation process, that may lead to better results, but also makes it more complicated. This paper presents the simple mathematical model for estimating the necessary FPGA resources to implement DA-LUT using decomposition-based approach. The model takes into account the type of logic cells or memory blocks used for decomposition process. The proposed model is helpful to determinate the DALUT decomposition strategy for further automation of modified distributed arithmetic decomposition method L1 - http://www.czasopisma.pan.pl/Content/87234/PDF/46.pdf L2 - http://www.czasopisma.pan.pl/Content/87234 PY - 2012 IS - No 4 DO - 10.2478/v10177-012-0046-y A1 - Rawski, Mariusz A1 - Staworko, MichaƂ PB - Polish Academy of Sciences Committee of Electronics and Telecommunications VL - vol. 58 DA - 2012 T1 - Modeling the Arithmetic Decomposition of DA-LUT Block for Heterogeneous FPGA Structures UR - http://www.czasopisma.pan.pl/dlibra/publication/edition/87234 T2 - International Journal of Electronics and Telecommunications ER -