TY - JOUR N2 - Digital system algorithms such as FFT algorithms, convolution, image processing algorithm, etc. deploy Multiply and Accumulate (MAC) unit as an evaluative component. The efficiency of a MAC typically relies on the speed of operation, power dissipation, and chip area along with the complexity level of the circuit. In this research paper, a power-delay-efficient signed-floating-point MAC (SFMAC) is proposed using Universal Compressor based Multiplier (UCM). Instead of having a complex design architecture, a simple multiplexer-based circuit is used to achieve a signed-floating output. The 8£8 SFMAC can take 8-bit mantissa and 3-bit exponent and therefore, the input to the SFMAC can be in the range of –(7.96875)10 to +(7.96875)10. The design and implementation of the proposed architecture is executed on the Cadence Spectre tool in GPDK 90 nm and TSMC 130 nm CMOS, which proves as power and delay efficient. L1 - http://www.czasopisma.pan.pl/Content/117264/PDF/20_835-844_01598_Bpast.No.68-4_27.08.20.pdf L2 - http://www.czasopisma.pan.pl/Content/117264 PY - 2020 IS - No. 4 (i.a. Special Section on Advances in Electrical Power Engineering) EP - 844 DO - 10.24425/bpasts.2020.134182 KW - floating-point MAC KW - UCM KW - cadence KW - TSMC 130 nm KW - GPDK 90 nm A1 - Sarma, R. A1 - Bhargava, C. A1 - Jain, S. VL - 68 DA - 31.08.2020 T1 - A MUX based signed-floating-point MAC architecture using UCM algorithm SP - 835 UR - http://www.czasopisma.pan.pl/dlibra/publication/edition/117264 T2 - Bulletin of the Polish Academy of Sciences Technical Sciences ER -