TY - JOUR N2 - In this paper, a new 11T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power. The cell shows improvement in RSNM (Read Static Noise Margin) with LP8T by 2.39x at sub-threshold voltage 2.68x with D6T SRAM cell, 5.5x with TG8T. The WSNM (Write Static Noise Margin) and HM (Hold Margin) of the SRAM cell at 0.9V is 306mV and 384mV. At sub-threshold operation also it shows improvement. The Leakage power reduced by 0.125x with LP8T, 0.022x with D6T SRAM cell, TG8T and SE8T. Also, impact of process variation on cell stability is discussed. L1 - http://www.czasopisma.pan.pl/Content/113323/PDF/81.pdf L2 - http://www.czasopisma.pan.pl/Content/113323 PY - 2019 IS - No 4 EP - 609 DO - 10.24425/ijet.2019.129819 KW - FinFET KW - RSNM KW - WSNM KW - Hold Margin KW - Subthreshold KW - Leakage Power A1 - Birla, Shilpi PB - Polish Academy of Sciences Committee of Electronics and Telecommunications VL - vol. 65 DA - 2019.11.03 T1 - Ultra-low Power FinFET SRAM Cell with Improved Stability Suitable for Low Power Applications SP - 603 UR - http://www.czasopisma.pan.pl/dlibra/publication/edition/113323 T2 - International Journal of Electronics and Telecommunications ER -